The present invention relates generally to digital circuits and, particularly, to a system and method for measuring the duty cycle of a high speed clocking signal.
In the specification of system clock signals provided for integrated circuits (ICs), the signal xe2x80x9cjitterxe2x80x9d is the most important specification. The second most important specification of a system clock in ICs is its duty cycle. The high frequency of the clock signals implemented in high-speed circuits prohibits measurement at the pins of the integrated circuit (IC). To overcome this, techniques for measuring frequency and jitter have implemented a divided clock. Unfortunately, the duty cycle information gets lost once the clock signal is divided down.
Particular prior art system s for measuring the duty cycle of a periodic signal have been described in U.S. Pat. No. 4.475,086, issued Mar. 31, 1982, and U.S. Pat. No. 5,367,200, issued Nov. 29, 1993. These systems rely on counter devices for measuring and, in the case of U.S. Pat. No. 4,475,086, implementing a higher frequency clock. An alternative technique is to measure the duty cycle at the wafer level which is very expensive and can only be done at the development cycle and not at the production level.
It would be highly desirable to provide a circuit that enables the measure of the duty cycle of a clock independent of its frequency.
It would be further highly desirable an integrated circuit provided with a clock measurement circuit that is designed for measuring and ensuring that that the duty signal of a clock signal meets its specification.
It is an object of the invention to provide a clock measurement circuit that provides a reliable and accurate means of measuring and ensuring that the clock duty cycle meets its specification.
It is a further object of the invention to provide a clock measurement circuit that provides a reliable and accurate means of measuring and ensuring that the clock duty cycle meets its specification independent of its frequency.
It is another object of the invention to provide a clock measurement circuit that measures the clock duty cycle independent of its frequency, and which may be implemented in an IC to enable testing at the production level.
According to the principles of the invention, there is provided a system and method for accurately measuring the duty cycle of an input periodic pulsed signal. The system comprises a device for converting the input signal to be measured into a first dc voltage; a device for encoding a plurality of duty cycle values for selection thereof in an iterative manner, one value of which represents a duty cycle of the input signal; a device for iteratively generating a second dc voltage according to a difference between the duty cycle of the input signal to be measured and the duty cycle represented by a current selected encoded duty cycle value; and a selection mechanism responsive to the first and second dc voltages for selecting an encoded duty cycle value for each iteration. The system selects an encoded duty cycle value in each successive iteration until the first and second dc voltages match. At such time, the current selected encoded duty cycle value represents the duty cycle of the input voltage for output thereof.
Advantageously, by representing the input signal""s duty cycle as a dc voltage, the system may measure the input signal""s duty cycle accurately regardless of its frequency as any error associated with its frequency is eliminated. Furthermore, the system may be incorporated in a phase lock loop (PLL) or a delay lock loop (DLL) within an IC itself, adding only a minor increase in silicon real estate.